EIE VLSI Lab 3 Verilog Sequence Detector Circuit (Compiled & Working on Quartus II v20.1)
EIE VLSI Lab #3 This article is to present a Verilog code for Sequence Detector using Moore FSM. A Verilog Testbench for the Moore FSM sequence detector is also provided for simulation below. The Moore FSM keeps detecting a binary sequence from a digital input and the output of the FSM goes high only when a "1011" sequence is detected. For a state diagram of the Moore FSM for the sequence detector, you might refer to the website at this hyperlink: https://www.fpga4student.com/2017/09/verilog-code-for-moore-fsm-sequence-detector.html You can also find some similar verilog files of the lab are placed in the Google Drive (hyperlink below), for reference: (you can just download the Quartus files) https://drive.google.com/drive/folders/1ARnWCZSUym3DMnA0rp0RT7bdNTfso2CN?usp=sharing Design Architecture: State Diagram (Click the picture to enlarge) Verilog code is designed as an example as follows: // ----- https://vlsiorfpgadesign.blogspot.com/...