EIE VLSI Lab 5 - VGA Controller (Compiled & working on Quartus v20.1)
EIE VLSI Lab 5 - VGA Controller (To be compiled on Quartus v20.1) Using Verilog Figure 1 VGA Controller Block Diagram (Click to enlarge) (Source: http://eewiki.net/pages/viewpage.action?pageId=15925278 ) Student is advised to refer to the schematic circuit daigram of the development board DE1-SoC. The onboard video chip DAC is ADV7123 (U5) which can output VGA signals to the VGA output connector (J9). Datasheet file of Video DAC: https://www.analog.com/media/en/technical-documentation/data-sheets/adv7123.pdf You could understand the principle from the above website of eewiki. (extracted diagram from the user manual of DE1-SoC) VGA Signal Timing Diagram Pin assignment of the I/Os to connect to control the video DAC chip: Files: 1) Design Verilog file VGA1_V.v : https://drive.google.com/file/d/1XA12FW6gY6i8q_aLBuW4yIvcuavr6OSD/view?usp=sharing 2) Pin assignment file VGA1_V.qsf : https://drive.google.com/file/d/1xmFU5P9cUuAP6X_dg25MHAfdfF8WSGYL/v...
