EIE511 Lab Info

  Laboratory Objectives The objectives of this laboratory are: l     Synthesize designs targeting a particular prototyping board l     Download a design to the FPGA prototyping board and have a fully functional design l     Understand the use constraint files l     Learn how to interface with the prototyping board through switches and buttons. Introduction The following design will output the 4 MSB of a 32-bit counter to 4 LEDs of the DE1-SoC prototyping board. By changing switch 8 of the board it should count UP or DOWN.   Terasic DE1-SoC Board The Terasic DE1-SoC prototyping board contains a single Cyclone V FPGA connected to a serious or peripherals and interconnects in order to communicate with other devices.   Terasic's DE1-SoC board contains the following major parts: 1) FPGA: l     Cyclone V SoC 5CSEMA5F31C6 Device l     Dual-core ARM Cortex-A9 (HPS) l     85K P...

  VLSI Lab 1 Lab 1: Design of Combinational Logic Designs using Schematic entry and Verilog using Quartus Prime Laboratory Objectives The objectives of this laboratory are: Learn how to use a commercially available FPGA synthesis environment. Create a combination circuit using graphical design entry (schematic entry) and Verilog. Analyze the synthesis results and understand the FPGA resources consumed. Simulate the design generating a testbench and verify the correctness of the simulation. Introduction This is a step-by-step tutorial for building a 1-bit full-adder using Quartus II Design Suite software that provides designers with the ability to generate digital circuits in different ways, e.g. schematic entry and/or using a hardware description language such as VHDL or Verilog. The Quartus II also provides the ability to apply FPGA pin and timing constraints, analyze for errors and violations. Full Adder An example 1-bit full adder block diagram and Boolean circuit are shown belo...

Intel (Altera) Terasic DE1-SoC Development Board (Cyclone V)    Video:  https://youtu.be/sKhvMhTiuM4 For the development board of Terasic development board DE1-SoC using Inter's (Altera) Cyclone V (28nm SoC 5CSEMA5F31C6N),  With ARM Cotex-A9 main processor, below are some tutorials for your references:  Tutorial 1a: Get started with Altera FPGA SoC and Linux Yocto on Terasic DE1-SoC dev board   Objectives: To learn how to configure HPS, add it into your FPGA project and establish communication between HPS and FPGA.  Procedures:  1) Create a new project and select your device (Cyclone V, 5CSEMA5F31)  2) Import the pin assignment  3) Open Qsyst and add HPS, other peripherals  4) Configure HPS  5) Add HPS components into your FPGA design - Dont forget to execute the TCL files  6) Create HPS header file by executing the "generate" file  7) Write your program and compile it using a makefile  8) Assign IP address ...