EIE511 Lab Info

    EIE VLSI Lab #3 This article is to present a Verilog code for Sequence Detector using Moore FSM. A Verilog Testbench for the Moore FSM sequence detector is also provided for simulation below.  The Moore FSM keeps detecting a binary sequence from a digital input and the output of the FSM goes high only when a "1011" sequence is detected. For a state diagram of the Moore FSM for the sequence detector, you might refer to the website at this hyperlink:  https://www.fpga4student.com/2017/09/verilog-code-for-moore-fsm-sequence-detector.html You can also find some similar verilog files of the lab are placed in the Google Drive (hyperlink below), for reference: (you can just download the Quartus files) https://drive.google.com/drive/folders/1ARnWCZSUym3DMnA0rp0RT7bdNTfso2CN?usp=sharing Design Architecture: State Diagram (Click the picture to enlarge) Verilog code is designed as an example as follows: // -----     https://vlsiorfpgadesign.blogspot.com/...

  Laboratory Objectives The objectives of this laboratory are: l     Synthesize designs targeting a particular prototyping board l     Download a design to the FPGA prototyping board and have a fully functional design l     Understand the use constraint files l     Learn how to interface with the prototyping board through switches and buttons. Introduction The following design will output the 4 MSB of a 32-bit counter to 4 LEDs of the DE1-SoC prototyping board. By changing switch 8 of the board it should count UP or DOWN.   Terasic DE1-SoC Board The Terasic DE1-SoC prototyping board contains a single Cyclone V FPGA connected to a serious or peripherals and interconnects in order to communicate with other devices.   Terasic's DE1-SoC board contains the following major parts: 1) FPGA: l     Cyclone V SoC 5CSEMA5F31C6 Device l     Dual-core ARM Cortex-A9 (HPS) l     85K P...